An Improved Modulation Method for Parallel Three-Level Rectifiers With Circulating Current Mitigation

An improved modulation method is proposed for two parallel three-level interleaved rectifiers to reduce current harmonics and high-frequency zero-sequence circulating current, which uses sinusoidal pulse width modulation. First, a model of the constructed, main factor affecting line performance discussed. Second, are priority optimization target guarantee better performance. Finally, an exchange large common-mode voltage between converters made high frequency based on low harmonics. Performance comparisons existing methods in terms total harmonics, value switching loss experiment, confirm effectiveness method.